The present invention relates generally to the fabrication of integrated circuits (IC""s), and more particularly to the fabrication of memory IC""s.
Semiconductor devices are used in a variety of electronic applications, such as personal computers and cellular phones, for example. One such semiconductor product widely used in electronic systems for storing data is a semiconductor memory, and one common type of semiconductor is a dynamic random access memory (DRAM).
A DRAM typically includes a large number of individual DRAM cells arranged in an array, with each cell storing one bit of data. A DRAM memory cell typically includes an access field effect transistor (FET) and a storage capacitor. The access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations. In addition, the data charges on the storage capacitor are periodically refreshed during a refresh operation.
The semiconductor industry in general is being driven to decrease the size of semiconductor devices located on integrated circuits. Miniaturization is generally needed to accommodate the increasing density of circuits necessary for today""s semiconductor products. As memory devices such as DRAMs are scaled down in size, various aspects of manufacturing DRAM IC""s are becoming more challenging. For example, extreme aspect ratios (the ratio of the vertical depth of a trench to the horizontal width) in small-scale devices present insulating gapfill and subsequent planarization process limitations. Aggressive aspect ratios in DRAM devices are approaching 4:1 and greater, for example. The gap fill requirement is a function of ground rule layout and critical dimension (CD) tolerances, as examples
FIG. 1 illustrates a cross-sectional view of a prior art DRAM 10 having closely nested features 2 and isolated features 4 having no minimum feature size and having no minimum distance apart. Often these two areas 2/4 are referred to as lines and spaces (L/S). The nested features 2 may comprise an array of densely-packed DRAM cells on minimum pitch, for example. Nested features 2 typically include lines and spaces that both comprise a minimum feature size, for example. Isolated features 4 also have the minimum pitch or feature size but are surrounded by a comparatively large space 6. Isolated features 4 are typically found in the peripheral circuitry of a DRAM layout, for example.
A substrate 12 is patterned with isolation trenches (IT""s) 15. The depth requirement of the isolation trenches is a function of the individual circuitry and depends on the requirement of providing sufficient electrical insulation either between devices or n- or p-doped wells for improved latch-up immunity, for example. The electrical insulation provided by the isolation trenches is often referred to as shallow trench isolation (STI).
STI regions typically function to separate the element regions of the DRAM array and define the outline of the vertical array device with a bitline contact, for example. The element regions may include active areas, storage capacitors and other electronic devices such as transistors. Besides providing the definition of bitline contact landing area in the vertical DRAM cell, the isolation trenches 15 also prevent cross-talk between two neighboring DRAM cells connected via the same wordline, for example. Preventing cross-talk in this manner ensures that only one cell is modified when being written to by accessing one row and a corresponding column in the DRAM array, for example.
A typical prior art process flow for achieving a high aspect ratio gapfill will next be described. A pad nitride 14 is deposited over the substrate 12 prior to the isolation trench 15 formation. The trenches 15 are filled with an insulator 16, which insulator 16 may comprise high-density plasma (HDP) oxide deposited by chemical vapor deposition (CVD), which has become a common material and isolation technique used in semiconductor device manufacturing. HDP oxide 16 typically forms peaks 22 (also referred to as huts or miters) over features. The HDP oxide huts 22 may cause a void 18 to form between high-aspect ratio features. The HDP oxide huts 22 xe2x80x98pinchxe2x80x99 off the flow of HDP oxide 16 into the trenches 15, thereby leading to incomplete gapfills. Incomplete gapfills become a problem in subsequent processing, for example, when a conductive layer is deposited on the wafer.
A problem in prior art isolation techniques is the formation of these voids 18 in high-aspect ratio trenches. As the minimum feature size is made smaller, the oxide gap fill of isolation trenches 15 becomes more challenging, especially in devices having vertical long channel transistors, for example. Leaving voids 18 in a finished semiconductor device results in device failures. Voids 18 may inadvertently be filled with conductive material in subsequent processing steps, for example.
Preventing the formation of voids 18 when an HDP oxide 16 insulator is used requires additional deposition steps: e.g., one or more additional HDP oxide deposition processes steps may be required in order to completely fill the trenches 15 to the top surface of the pad nitride 14. The HDP oxide 16 may be etched back to the top of the pad nitride 14, and at least one additional layer of HDP oxide (not shown) may be deposited and etched back until the trenches 15 are filled. Conductive material left in voids exposed after CMP processing steps may enter the trenches 15 and short elements in the substrate 12.
What is needed in the art is a method of filling isolation trenches 15 of a DRAM cell that minimizes the number of insulating layers 16 required to be deposited and prevents possible shorting of elements in the substrate 12.
The present invention provides a method of filling isolation trenches of a semiconductor device.
In accordance with a preferred embodiment, disclosed is a method of isolating active areas of a semiconductor memory device, the memory device including a plurality of trenches separating a plurality of element regions, the method comprising depositing a first insulating material over the trenches, the first insulating material comprising a first top portion and a second top portion. A resist is formed over the first insulating material over at least the trenches, leaving the first top portion of the first insulating material exposed. At least the second top portion of the first insulating material is removed.
In accordance with a preferred embodiment, also disclosed is a method of manufacturing a memory device, comprising providing a semiconductor wafer having a substrate, forming isolation trenches between substrate element regions, and depositing a first insulating material over the trenches, the first insulating material including a first top portion and a second top portion, the second top portion being larger than the first top portion. A resist is formed over portions of the trenches, leaving the first insulating material first top portion exposed, and at least the second top portion of the first insulating material is removed.
In accordance with a preferred embodiment, disclosed is a method of isolating element regions of a semiconductor wafer, comprising forming trenches between element regions, forming a first HDP oxide layer over the trenches, the first HDP oxide layer including huts, forming a resist over at least the trenches leaving a top portion of the first HDP oxide layer huts exposed, removing at least the first HDP oxide layer huts, and removing the resist.
Advantages of embodiments of the invention include providing a process flow in which the removal of insulating material within isolation trenches is self-aligned, and does not require an additional mask. The number of insulating material deposition steps is reduced in accordance with an embodiment of the present invention. A pad nitride layer and liner may serve as an etch stop during removal of the top portion of the first insulating material deposited, and an optional nitride liner provides increased processing parameters.